Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Opening: Analog Circuit Design

Roles: Principal Engineer

Experience: 10-17+ Years
Location: Hyderabad (Preferred) / Noida / Pune
Education: BE / B.Tech / ME / M.Tech / MS

Join a team building next-generation UCIe, D2D, PCIe, DDR/LPDDR, HBM, GDDR, and SerDes IPs on advanced technology nodes.

Key Responsibilities

• Architect, design, and deliver high-speed Analog/Mixed-Signal IPs and subsystems.
• Drive design closure for TX/RX, PLL, DLL, CDR, Clocking, Datapath, I/O, and interface circuits.
• Lead complex IP programs involving cross-functional teams including Analog Design, Layout, AMS Verification, Digital, and Physical Design.
• Mentor engineers and drive technical excellence, innovation, and execution.
• For management roles, lead project execution, staffing, risk management, and customer engagements.

• Strong expertise in high-speed interface design:
  • UCIe / Die-to-Die (D2D)
  • PCIe Gen3/4/5/6
  • DDRx / LPDDRx / GDDRx / HBM
  • High-speed SerDes architectures
• Strong Analog Design and I/O fundamentals.
• Knowledge of SI/PI, ESD, Reliability, Jitter, Timing, and PPA optimization.
• Experience delivering complex IPs from architecture to silicon.
• Excellent communication, leadership, and problem-solving skills.

• Experience with advanced technology nodes (16nm, 12nm, 10nm, 7nm, 5nm, 3nm).
• Experience in IP architecture, technology migration, and design reuse methodologies.
• Proven track record of leading large technical teams and delivering high-performance connectivity or memory interface solutions.

Cadence is a pivotal leader in computational software, delivering software, hardware, and IP that our customers use to turn design concepts into reality for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and life sciences.