Engineering Director - Subsystem Interoperability & AI-Driven Verification

Location: Bengaluru, India

Job Description and Requirements Job Title: - Engineering Director - Subsystem Interoperability & AI-Driven VerificationWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent two decades building verification teams and solving the problems that live between IP blocks, where clean interfaces meet messy reality and independently verified components refuse to cooperate. The gap between a Controller that passes all tests and a Controller-PHY-firmware combination that actually works in a customer SoC is where you live, and you have built the instincts to close it.You are technical enough to review a UVM testbench, debug a protocol violation three layers deep, and make the call on whether a coverage hole is real or academic. But you also know that verification at scale is not about heroic debug sessions, it is about building systems that catch problems before they become customer issues. You think in factories, not fire drills.What excites you now is applying AI to verification work that has resisted automation for years. You see LLMs, agentic workflows, and intelligent orchestration not as buzzwords but as tools that can finally turn interoperability from a bottleneck into a continuously running capability. You are ready to build that capability from the ground up at Synopsys, where the IP portfolio is real, the customer stakes are high, and the technical challenge is exactly the kind you have been preparing for.What You'll Be DoingBuild and lead the Central Interoperability team from scratch, defining its technical strategy, organizational structure, verification methodology, execution model, and success metrics across high-speed interface IPs including UCIe, PCIe, CXL, DDR, HBM, Ethernet, and USBOwn end-to-end Controller-PHY interoperability qualification, from UVM environment bring-up and configuration management through verification execution, functional and structural coverage closure, protocol compliance, debug, and generation of customer-ready release evidenceEstablish an always-on Interop Factory where new Controller, PHY, or firmware releases automatically trigger integration, regression suites, qualification workflows, and evidence generation without manual interventionDrive interoperability verification beyond basic connectivity into protocol compliance, stress and error injection scenarios, CDC/RDC checks, timing constraints validation, and implementation readiness across the Controller × PHY × Firmware × VIP × Configuration state spaceMake the factory AI-native by applying LLMs, AI agents, RAG, MCP, and intelligent workflow orchestration to environment generation, test plan development, regression selection, failure clustering, root-cause analysis, debug acceleration, and knowledge reuse across releasesBuild a continuous learning loop where customer issues feed directly into root-cause analysis, prevention test creation, regression integration, and future release qualification, systematically converting field learning into improved product qualityPartner across Controller and PHY R&D teams, architecture, VIP development, firmware, methodology, applications engineering, and product management to create one accountable, transparent subsystem-readiness view for every releaseThe Impact You Will HaveYou will create a new verification capability that shifts interoperability left in the development cycle, reducing subsystem bring-up time for customers and increasing the number of qualified Controller-PHY-firmware configurations available at releaseYou will transform interoperability from a customer integration exercise into a continuously verified product capability, with reusable qualification evidence and clear release gates that reduce field issues and support escalationsYour factory will establish a scalable blueprint for subsystem verification across the broader Synopsys IP portfolio, creating reusable infrastructure, methodology, and AI-enabled automation that other teams can adoptYou will build a team culture that attracts top verification talent, mentors engineers into technical leadership roles, and keeps the organization technically engaged even as it scalesYou will make AI-assisted verification real and measurable, demonstrating how LLMs and agentic workflows can accelerate debug, improve coverage strategies, and turn tribal knowledge into reusable intelligenceYou will create predictable, data-driven subsystem readiness visibility for executives and customers, replacing subjective assessments with objective qualification metrics tied to real verification evidenceYou will reduce the time from IP release to customer-ready subsystem from months to weeks by automating the integration, qualification, and evidence-generation workflows that currently require manual coordinationWhat You'll Need20+ years of semiconductor design and verification experience with significant technical leadership responsibility building and scaling verification teamsDeep expertise in ASIC, SoC, IP, or subsystem verification using SystemVerilog, UVM, verification planning, functional and code coverage analysis, assertions, regression infrastructure, and complex multi-IP debugStrong hands-on experience with high-speed protocols such as UCIe, PCIe, CXL, DDR, HBM, Ethernet, USB, or SerDes, including protocol compliance, Controller-PHY integration, and interoperability challengesProven track record integrating independently developed IP blocks and driving complex cross-functional technical programs across R&D, product, and applications teamsStrong scripting and automation skills using Python, Tcl, or equivalent for building verification infrastructure, regression frameworks, and intelligent workflow orchestrationExperience with CDC/RDC verification, formal methods, emulation or prototyping platforms, CI/CD for verification, or physical implementation flows is highly desirableExposure to LLMs, agentic AI, RAG, MCP, AI-assisted verification or debug tools, or intelligent engineering automation is strongly preferred and will differentiate your applicationWho You AreYou can sit in a technical review with verification engineers debugging a CXL protocol failure and walk out with a clear action plan, then turn around and explain the customer-readiness risk to a VP in two sentences without losing the technical nuanceYou do not wait for perfect alignment across teams to get started, you define the interoperability strategy, build the initial environment, and prove the value before asking for full organizational buy-inYou recruit engineers who are better than you at specific things and you create the conditions for them to do their best work, whether that is deep UVM expertise, AI automation, or protocol-level debugYou have a point of view on what good verification looks like and you push back when a test plan is too shallow, a coverage model is missing critical scenarios, or a release gate is being bypassed without real justificationYou are energized by building new capabilities from scratch, not inheriting mature organizations, and you are comfortable with the ambiguity, cross-functional negotiation, and technical problem-solving that comes with thatYou stay technical, you still read code, review testbenches, understand coverage reports, and debug failures alongside your team, because that is how you earn credibility and make good decisionsThe Team You'll Be Part OfYou will build the Central Subsystem Interoperability team from the ground up, establishing its charter, hiring its engineers, and defining its relationship to Controller R&D, PHY R&D, VIP, firmware, and product teams across Synopsys. This is a new capability being created to transform how independently developed IP becomes qualified, customer-ready subsystems. You will report into senior engineering leadership and work closely with architecture, methodology, and product management to establish the vision, execution model, and success metrics for this organization. Your team will become the accountable owner of subsystem readiness across high-speed interface IPs, with the mandate to build an always-on, AI-enabled interoperability factory that scales across the portfolio.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.