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Principal/Senior Manager ASIC Verification

Weekday

Full time On-site
Experience
10 years
Location
Hyderabad
Work mode
On-site
Posted 6 days ago Last checked 19 min ago

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Role at a glance

Experience
10 years
Work mode
On-site

Job description

Location: Hyderabad, India

The Senior Manager of digital design and digital verification leads a team responsible for designing/verifying complex mixed-signal ICs that integrate Analog & digital components. This role demands deep technical expertise, strategic leadership, and cross-functional collaboration to ensure first-pass silicon success Your role Key responsibilities in your new role Architecture and design of digital blocks for integration CMOS IC’s Specification and design of digital blocks at RTL level and addition of DfT concept onto the design Synthesis, block verification and gate level analysis of implemented digital blocks for on-silicon integration Implementation and verification of ECO’s on existing designs Technically lead digital design tasks in strong cooperation with project technical lead and project manager Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Manage and mentor a team of digital and digital DV engineers. Drive hiring, performance reviews, and career development. Foster a culture of technical excellence and innovation. Your profile Qualifications and skills to help you succeed Master’s or PhD in Electrical Engineering or related field. 10+ years of experience in mixed-signal IC verification, with 3–5 years in a leadership role. Knowledge of relevant digital design flow tools for synthesis, LEC (logic equivalence check), CDC/RDC (clock/reset domain crossing), linting, synthesis constraining Proficiency in Verilog, Verilog-A/AMS, UVM, and scripting languages (Python, Perl, Tcl). #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon.

Job data: Headcount Labs (headcountlabs.com), ODbL 1.0. The job description belongs to the employer. Location data © OpenStreetMap contributors and Overture Maps.

Job market insights

65 more open jobs at Weekday

Most Engineering Jobs posts in Hyderabad ask for 6–10 years of experience (37% of 52 that say).

Hiring most for Engineering Jobs in Hyderabad

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From live job posts on CoreHRx, updated 10 Nov 2026. Skill figures count posts that list their skills; salary figures only posts that show a salary.

Questions about this job

How much experience does this job need?

The post asks for 10 Yrs experience.

Where is this job based?

In Hyderabad (on-site).

What kind of job is this?

It is a full time job.

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