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Experience: 5 10 Years
Location: Bengaluru
Work Mode: Work from office
Notice Period: Immediate to 30 Days
Domain: Semiconductor | Analog/Mixed-Signal | EDA | Circuit Simulation & Verification
1. Role OverviewWe are looking for an experienced Senior Analog/Mixed-Signal (AMS) Simulation & Verification Engineer with strong hands-on expertise in analog circuit simulation, mixed-signal verification, behavioral modeling and EDA simulation environments.
The role involves configuring, validating and debugging simulation setups using Cadence Virtuoso ADE, Spectre and Synopsys PrimeSim, including advanced circuit analyses, PVT corners and Monte Carlo simulations.
The engineer will be responsible for mixed-signal (RTL + analog) co-simulation, simulation automation and behavioral model development, while collaborating with AI/EDA software teams to improve automated simulation workflows.
2. Key ResponsibilitiesReview and validate analog/mixed-signal simulation setups, including testbench connectivity, stimuli, model files, corner configurations, simulator options and measurement expressions.
Configure and execute simulations using Cadence Virtuoso ADE L, ADE XL, ADE Assembler, ADE Explorer and Spectre simulation environments.
Perform DC Operating Point, AC, Transient, Stability, Noise, Monte Carlo and other advanced circuit simulation analyses.
Work with Synopsys PrimeSim, HSPICE, PrimeWave and related circuit simulation environments.
Develop and validate analog behavioral models using Verilog-A, Verilog-AMS and SystemVerilog Real Number Modeling (RNM).
Implement mixed-signal co-simulation integrating Verilog, SystemVerilog or VHDL RTL with transistor-level and behavioral analog blocks.
Configure and debug Cadence Xcelium/Spectre AMS Designer and Synopsys VCS/PrimeSim mixed-signal simulation flows.
Manage foundry PDK model libraries, PVT corners, statistical models, Monte Carlo simulations and parametric sweeps.
Investigate simulator convergence failures, numerical accuracy issues, runtime performance and analog-digital interface problems.
Develop simulation automation, measurement extraction and regression workflows using OCEAN/SKILL, Python, Tcl and shell scripting.
Analyze simulation results using ADE Calculator, PSF, FSDB and other waveform or simulation data formats.
Document simulation methodologies, verification checklists and reference results while collaborating with AI/EDA development teams.
5 10 years of hands-on experience in Analog/Mixed-Signal (AMS) Circuit Simulation and Verification.
Strong practical experience with Cadence Virtuoso ADE L, ADE XL or ADE Assembler and Spectre.
Working knowledge of Synopsys PrimeSim, HSPICE and PrimeWave.
Hands-on experience in mixed-signal RTL and analog co-simulation.
Experience with Cadence AMS Designer/Xcelium or Synopsys VCS/PrimeSim mixed-signal simulation flows.
Experience developing behavioral models using Verilog-A, Verilog-AMS and/or SystemVerilog RNM.
Strong understanding of DC, AC, Transient and Stability simulation analyses and advanced simulator settings.
Knowledge of foundry PDK models, PVT corners, statistical models and Monte Carlo simulations.
Understanding of analog circuit fundamentals, including amplifiers, LDOs, bandgaps, comparators, data converters, PLLs and filters.
Experience with simulation automation using OCEAN/SKILL, Python, Tcl or shell scripting.
Strong UNIX/Linux command-line proficiency.
A. Analog Simulation Tools
Cadence Virtuoso ADE L / ADE XL
Cadence ADE Assembler / ADE Explorer
Cadence Spectre / Spectre APS / Spectre X
Synopsys PrimeSim / HSPICE
Synopsys PrimeWave / Custom Compiler
B. Circuit Simulation & Analysis
DC Operating Point (OP/DC)
AC Analysis
Transient Analysis
Stability Analysis (STB)
Noise Analysis
Monte Carlo Simulation
Parametric Sweeps
PVT Corner Analysis
Advanced Analyses: PSS, PAC, PNoise, PXF, PSTB, HB, HBAC, HBNoise, SP and DCMatch
C. Mixed-Signal Verification
Analog/Mixed-Signal (AMS) Co-Simulation
Cadence Xcelium / Spectre AMS Designer
Synopsys VCS / PrimeSim
RTL + Analog Co-Simulation
Verilog / SystemVerilog / VHDL
Analog-Digital Interface Debugging
Connect Modules and Simulation Partitioning
D. Behavioral Modeling
Verilog-A
Verilog-AMS
SystemVerilog Real Number Modeling (RNM)
Analog Behavioral Model Development
Behavioral Model vs. Transistor-Level Correlation
E. PDK & Simulation Methodology
Foundry PDK Models
Model Libraries and Corner Sections
Process Variation and Mismatch Analysis
Monte Carlo and Statistical Simulation
Simulator Convergence and Accuracy Optimization
RelTol, AbsTol, MaxStep, Gmin and Tstab Configuration
F. Automation & Scripting
Cadence OCEAN / SKILL
Python
Tcl
Shell Scripting
ADE Calculator
PSF / FSDB Data Extraction
Simulation Regression Automation
UNIX / Linux
Most IT Jobs posts in Bangalore ask for 3–6 years of experience (41% of 4026 that say).
From live job posts on CoreHRx, updated 12 Nov 2026. Skill figures count posts that list their skills; salary figures only posts that show a salary.
The post does not state the pay. As an estimate, comparable posts on CoreHRx advertise ₹15L – ₹25L a year (typical for IT Jobs in Bangalore, 263 posts).
The post asks for 10 Yrs experience.
In Bangalore (on-site).
It is a full time job.
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